1. Technical Field
This invention generally relates to computer memory systems, and more specifically relates to optimizing read/modify/write control in a computer memory system.
2. Background Art
Since the dawn of the computer age, computer systems have evolved into extremely sophisticated devices that may be found in many different settings. Computer systems typically include a combination of hardware (e.g., semiconductors, circuit boards, etc.) and software (e.g., computer programs). One key component in any computer system is memory.
Modern computer systems typically include dynamic random-access memory (DRAM). DRAM is different than static RAM in that its contents must be continually refreshed to avoid losing data. A static RAM, in contrast, maintains its contents as long as power is present without the need to refresh the memory. This maintenance of memory in a static RAM comes at the expense of additional transistors for each memory cell that are not required in a DRAM cell. For this reason, DRAMs typically have densities significantly greater than static RAMs, thereby providing a much greater amount of memory at a lower cost than is possible using static RAM.
However, DRAMs are also more prone to errors in the data read from the memory. Sophisticated error correction circuitry has been developed that allow detecting errors in a DRAM. During a typical read cycle, a cache line is read, causing a corresponding read of an error correction code (ECC) from memory. The error correction circuitry uses the ECC to detect if there are errors in the data within the ECC boundary. The ECC boundary is the amount of data or size of the chunk of memory used to generated the ECC (such as a cache line). When data is written to memory the error correction circuitry generates the ECC, which is then written to the cacheline with the data, and then into the memory.
Modern DRAM memory controllers support a memory command known as Read/Modify/Write (RMW). A RMW command is used to write less data than a full cache line. Before the write operation, the full cache line of data must be read to be combined with the new data of the RMW command. This is necessary to assure data integrity in the memory and so that a new error correction code can be generated for the store. In the prior art, once the RMW cycle starts, the entire RMW sequence is performed as an atomic operation to assure data integrity. If processor reads occur just after the read operation of the RMW cycle, the processor reads have to wait until the atomic RMW operation is completed. As a result, prior art memory controllers negatively affect system performance when performing Read/Modify/Write operations due to excessive time spent processing RMW operations. Without a way for performing Read/Modify/Write operations in a way that does not make processor read cycles wait, the computer industry will continue to be plagued with decreased performance during Read/Modify/Write cycles.